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AREA AND POWER EFFICIENCY OF CARRY SELECT ADDER USING GATE DIFFUSION INPUT(GDI) LOGIC
Subject area: Science,Engineering and Technology · Area of research: VLSI
Abstract
In this paper an area and power efficient design of 8 bit Carry Select Adder (CSLA) has been proposed. Conventional and other CSLAs are designed using CMOS technology, which has complexity in terms of area and power consumption. So to overcome this problem a new technology is implemented on the CSLA. This paper shows the implementation and comparison of Carry Select Adder (CSA) using BEC (Binary Excess one Converter) and First Zero Finding (FZF) logic implementation techniques with optimization of GDI Logic by minimize number of transistors. All the designs are implemented 1.8 Volt power supply and 180 nm technology in Cadence Virtuoso environment.
Keywords
Carry Select Adder (CSLA); GDI (Gate Diffusion Input); RCA (Ripple Carry Adder); MUX (Multiplexer); BEC (Binary to Excess one Convertor); FZF(First Zero Finding
References
[1] B. Ramkumar and Harish M Kittur, "Low – Power and Area-Efficient Carry Select Adder", IEEE TRANSACTIONS ON VLSI SYSTEMS, Vol. 20, February 2012.
[2] Basant Kumar Mohanty and Sujit Kumar Patel, “Area–Delay–Power Efficient Carry-Select Adder”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, Vol. 61, No. 6, JUNE 2014
[3] S. A. Mashankar, R. D. Kadam and P. R. Indurkar, “Power Efficient Carry Select Adder using D-Latch”, IRJET, Vol. 02, Issue: 03, June 2015
[4] O. J. Bedrij, “Carryselect adder,” IRE Trans. Electron, Comput., vol. EC-11, no. 3, pp. 340- 344,Jun. 1962
[5] Edison A.J and C.S Manikandababu, “An Area Efficient CSLA Architecture for VLSI Hardware Implementation”, IJMIE, Vol. 2, Issue 5, May 2012
[6] Prashanth Gurjar, Rashmi Solanki, Pooja Kansliwal and Mahendra Vucha, “VLSI Implementation of Adders for High Speed ALU”, International Journal of Computer Applications, Volume 10 – No 29, September 2011
[7] Arkadiy Morgenshtein, Alexander Fish and Israel A. Wagner, “Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinational Circuits”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 10, No. 5, October 2002
How to cite this paper
@article{1701369,
author = {SANGEETHA K, KAYALVIZHI S},
title = {AREA AND POWER EFFICIENCY OF CARRY SELECT ADDER USING GATE DIFFUSION INPUT(GDI) LOGIC},
journal = {Iconic Research And Engineering Journals},
year = {2019},
volume = {3},
number = {1},
pages = {143-147},
issn = {2456-8880},
url = {https://www.irejournals.com/formatedpaper/1701369.pdf},
abstract = {In this paper an area and power efficient design of 8 bit Carry Select Adder (CSLA) has been proposed. Conventional and other CSLAs are designed using CMOS technology, which has complexity in terms of area and power consumption. So to overcome this problem a new technology is implemented on the CSLA. This paper shows the implementation and comparison of Carry Select Adder (CSA) using BEC (Binary Excess one Converter) and First Zero Finding (FZF) logic implementation techniques with optimization of GDI Logic by minimize number of transistors. All the designs are implemented 1.8 Volt power supply and 180 nm technology in Cadence Virtuoso environment.},
keywords = {Carry Select Adder (CSLA); GDI (Gate Diffusion Input); RCA (Ripple Carry Adder); MUX (Multiplexer); BEC (Binary to Excess one Convertor); FZF(First Zero Finding},
month = {July},
}