Design of Approximate Multiplier to Reduce Delay and Area

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@article{1703285,
      author = {Sulakshana W},
      title = {Design of Approximate Multiplier to Reduce Delay and Area},
      journal = {Iconic Research And Engineering Journals},
      year = {2022},
      volume = {5},
      number = {9},
      pages = {354-358},
      issn = {2456-8880},
      url = {https://www.irejournals.com/formatedpaper/1703285.pdf},
      abstract = {The key idea of approximate computing is to trade off accuracy in computation, for better performance and energy efficiency. Many important applications such as, multimedia signal processing and image processing applications etc. can essentially tolerate inaccurate computation. Approximate com- putting has the ability to tolerate lack of accuracy and soft errors found in many applications to gain remarkable energy. It can provide considerable reductions in circuit complexity, delay, area and energy consumption by easing accuracy requirements. In this paper, we propose approximate multiplier design with 32-bits using Vedic multiplier and altered partial product, that demonstrate reduced area and shorter critical path delay than the conventional multiplier. The proposed design is analyzed using Xilinx.},
      keywords = {Approximate computing, approximate multi- plier, approximate compressors, approximate adders.},
      month = {March},
  }