AI-Native Semiconductor Engineering: Reinforcement Learning, Graph Neural Networks, and Digital Twins as Core Design Infrastructure

References

[1] International Technology Roadmap for Semiconductors (ITRS), "ITRS 2.0: 2015 Edition," ITRS, 2015. [Online]. Available: http://www.itrs2.net/

[2] Semiconductor Industry Association (SIA), "2025 State of the U.S. Semiconductor Industry," SIA, Washington, DC, Jul. 2025. [Online]. Available: https://www.semiconductors.org/2025-state- of-the-industry-report-investment-and- innovation-amidst-global-challenges-and- opportunities/

[3] Semiconductor Industry Association (SIA), "Global Annual Semiconductor Sales Increase 25.6% to $791.7 Billion in 2025," SIA, Washington, DC, Feb. 6, 2026. [Online]. Available: https://www.semiconductors.org/global- annual-semiconductor-sales-increase-25-6-to- 791-7-billion-in-2025/

[4] Deloitte, "2026 Global Semiconductor Industry Outlook," Deloitte Insights, Feb. 2026. [Online]. Available: https://www.deloitte.com/us/en/insights/indust ry/technology/technology-media-telecom- outlooks/semiconductor-industry-outlook.html

[5] Semiconductor Industry Association (SIA) and Oxford Economics, "Chipping Away: Assessing and Addressing the Labor Market Gap Facing the U.S. Semiconductor Industry," SIA, Washington, DC, Jul. 2023. [Online]. Available: https://www.semiconductors.org/chipping- away-assessing-and-addressing-the-labor- market-gap-facing-the-u-s-semiconductor- industry/

[6] M. M. Waldrop, "The chips are down for Moore's law," Nature, vol. 530, no. 7589, pp. 144–147, Feb. 2016.

[7] A. Mirhoseini, A. Goldie, M. Yazgan, J. W. Jiang, E. Songhori, S. Wang, Y.-J. Lee, E. Johnson, O. Pathak, A. Nazi, J. Pak, A. Tong, K. Srinivasa, W. Hang, E. Tuncer, Q. V. Le, J. Laudon, R. Ho, R. Carpenter, and J. Dean, "A graph placement methodology for fast chip design," Nature, vol. 594, no. 7862, pp. 207– 212, Jun. 2021. 03544-w

[8] D. S. Lopera, L. Servadei, G. N. Kiprit, S. Hazra, R. Wille, and W. Ecker, "A survey of graph neural networks for electronic design automation," in Proc. 3rd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2021, pp. 1 –6. 10.1109/MLCAD53597.2021.9531070

[9] R. Chen et al., "Graph computation meets circuit algebra: A task-aligned analysis of graph neural networks for electronic design automation," arXiv:2605.08291, May 2025. [Online]. Available: https://arxiv.org/html/2605.08291v1

[10] Synopsys Inc., "DSO.ai: Autonomous AI- driven design space optimization," Synopsys. [Online]. Available: https://www.synopsys.com/implementation- and-signoff/ml-ai-driven-design/dso-ai.html

[11] Cadence Design Systems Inc., "Cerebrus Intelligent Chip Explorer," Cadence. [Online]. Available: https://www.cadence.com/en_US/home/tools/ digital-design-and-signoff/silicon- signoff/cerebrus-intelligent-chip-explorer.html

[12] Google Research, "Circuit Training: An Open- Source Framework for Generating Chip Floor Plans with Distributed Deep Reinforcement Learning," GitHub, 2021. [Online]. Available: https://github.com/google- research/circuit_training

[13] Y. Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan, "DREAMPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 40, no. 4, pp. 748–761, Apr. 2021. 10.1109/TCAD.2020.3003843

[14] R. Cheng and J. Yan, "On joint learning for solving placement and routing in chip design," in Proc. 35th Conf. Neural Inf. Process. Syst. (NeurIPS), 2021. [Online]. Available: https://arxiv.org/abs/2111.00234

[15] Siemens Digital Industries Software, "Unlocking the Future with a Digital Twin for Semiconductor Manufacturing," Siemens Calibre Blog, Mar. 29, 2024. [Online]. Available: https://blogs.sw.siemens.com/calibre/2024/03/ 29/unlocking-the-future-with-a-digital-twin- for-semiconductor-manufacturing/

[16] Tokyo Electron Ltd. (TEL), "Digital Twins Accelerate Innovation in Semiconductor Technology," TEL Blog, Aug. 28, 2025. [Online]. Available: https://www.tel.com/blog/all/20250828_001.h tml

[17] Lam Research Corp., "Revolutionizing Chipmaking: The Power of Digital Twins in Semiconductor Manufacturing," Lam Research Newsroom. [Online]. Available: https://newsroom.lamresearch.com/how- digital-twins-can-revolutionize-chipmaking

[18] Synopsys Inc., "Digital Twins for the Semiconductor Industry," Synopsys Blog. [Online]. Available: https://www.synopsys.com/blogs/chip- design/digital-twins-semiconductor- industry.html

[19] R. Laubscher et al., "Generative and predictive AI for digital twin systems in manufacturing," PMC / NCBI, 2025. [Online]. Available: https://www.ncbi.nlm.nih.gov/pmc/articles/P MC12753877/

[20] C.-K. Cheng, A. B. Kahng, S. Kundu, Y. Wang, and Z. Wang, "An updated assessment of reinforcement learning for macro placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., early access, Dec. 2025. 10.1109/TCAD.2025.3545001. [Online]. Available: https://ieeexplore.ieee.org/document/1130030 4; code/benchmarks: https://github.com/TILOS-AI- Institute/MacroPlacement

[21] Anonymous authors, "Physics -guided geometric diffusion for macro placement generation (MacroDiff+)," arXiv:2605.16451, 2025/26. [Online]. Available: https://arxiv.org/pdf/2605.16451

[22] C.-K. Cheng, A. B. Kahng, I. Markov, and J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, 2nd ed. Springer, 2022. 96415-3

[23] Semiconductor Industry Association (SIA), "2025 SIA Factbook," SIA, Washington, DC, May 2025. [Online]. Available: https://www.semiconductors.org/wp- content/uploads/2025/05/2025-SIA-Factbook- FINAL-1.pdf

[24] G. Huang et al., "Machine learning for electronic design automation: A survey," ACM Trans. Design Autom. Electron. Syst., vol. 26, no. 5, pp. 1–46, 2021. 10.1145/3451179

[25] J. Gu et al., "A comprehensive survey on electronic design automation and graph neural networks," ACM Trans. Design Autom. Electron. Syst., vol. 28, no. 2, 2023. 10.1145/3543853

[26] Semiconductor Industry Association (SIA), "Semiconductor Workforce Policy Blueprint," SIA, Washington, DC, Apr. 2024. [Online]. Available: https://www.semiconductors.org/wp- content/uploads/2024/04/SIA-Workforce- Policy-Blueprint-4_8_24.pdf

[27] CHIPS and Science Act of 2022, Pub. L. No. 117-167, 136 Stat. 1366, Aug. 9, 2022. [Online]. Available: https://www.congress.gov/bill/117th- congress/house-bill/4346

@article{1722423,
      author = {Arnav Butail},
      title = {AI-Native Semiconductor Engineering: Reinforcement Learning, Graph Neural Networks, and Digital Twins as Core Design Infrastructure},
      journal = {Iconic Research And Engineering Journals},
      year = {2026},
      volume = {10},
      number = {2},
      pages = {2319-2334},
      issn = {2456-8880},
      url = {https://www.irejournals.com/formatedpaper/1722423.pdf},
      abstract = {At sub-5 nm process nodes, traditional semiconductor scaling is coming up against physical and economic limits, with Moore's Law no longer applicable. At the same time, the need for computation power is increasing and growing every day with the advent of Artificial Intelligence (AI), 5G/6G communications and autonomous systems. In this survey paper, we suggest that the semiconductor design industry is in a structural shift to an AI native paradigm, where reinforcement learning (RL), graph neural networks (GNNs), digital twins, and agentic orchestration frameworks are key and not auxiliary parts of the chip design flow. This paper: (i) reviews the physical, economic and workforce pressures driving the transition; (ii) summarizes the results of a survey of demonstrated work in RL for floor planning and placement, GNN for EDA prediction and digital-twin enabled pre-fabrication validation; (iii) categorizes placement methodologies and their evaluation protocols; (iv) presents a detailed technical decomposition of each AI-native pillar; (v) analyses the economic case for investing in AI-native design; (vi) discusses open research challenges and four tractable directions along which this research will progress; and (vii) suggests a roadmap for a four-stage curriculum for preparing the next-generation semiconductor engineer. The analysis shows that learned placement methods can be competitive with, but do not yet consistently outperform, well-designed classical placement algorithms, confirming that the need for well-designed classical placement algorithms remains crucial as AI-native tools approach production use.},
      keywords = {artificial intelligence, chip design, deep reinforcement learning, digital twin, electronic design automation, floor planning, graph neural networks, hardware-software co-design, moore's law, semiconductor engineering, simulated annealing, vlsi placement, yield prediction.},
      month = {August},
      doi = {https://doi.org/10.64388/IREV10I2-1722423}
  }