A Novel Step-Up Multilevel Inverter

References

[1] NL

[2] NIS

[3] NS

[4] ND

[5] NAD

[6] NGD

[7] NC

[8] Component count per level

[9] [2]

[10] 5

[11] 1

[12] 9

[13] 9

[14] 0

[15] 9

[16] 1

[17] 5.600

[18] [3]

[19] 9

[20] 1

[21] 10

[22] 10

[23] 1

[24] 8

[25] 2

[26] 3.444

[27] [4]

[28] 9

[29] 1

[30] 12

[31] 12

[32] 0

[33] 11

[34] 2

[35] 4.111

[36] [5]

[37] 7

[38] 1

[39] 10

[40] 10

[41] 0

[42] 10

[43] 2

[44] 4.571

[45] [6]

[46] 5

[47] 1

[48] 6

[49] 6

[50] 2

[51] 6

[52] 1

[53] 4.200

[54] [7]

[55] 7

[56] 1

[57] 16

[58] 16

[59] 0

[60] 14

[61] 2

[62] 6.857

[63] [8]

[64] 5

[65] 1

[66] 6

[67] 6

[68] 2

[69] 6

[70] 2

[71] 4.400

[72] [9]

[73] 5

[74] 1

[75] 9

[76] 9

[77] 1

[78] 8

[79] 1

[80] 5.600

[81] [10]

[82] 5

[83] 1

[84] 6

[85] 6

[86] 1

[87] 6

[88] 1

[89] 5.000

[90] [11]

[91] 5

[92] 2

[93] 8

[94] 8

[95] 0

[96] 8

[97] 0

[98] 4.800

[99] [12]

[100] 5

[101] 1

[102] 12

[103] 12

[104] 0

[105] 12

[106] 2

[107] 7.600

[108] [13]

[109] 5

[110] 1

[111] 7

[112] 7

[113] 3

[114] 7

[115] 2

[116] 5.200

[117] [16]

[118] 9

[119] 1

[120] 11

[121] 11

[122] 0

[123] 10

[124] 2

[125] 3.777

[126] Proposed

[127] 13

[128] 1

[129] 14

[130] 14

[131] 0

[132] 13

[133] 3

[134] 3.384

[135] Table III

[136] Comparison of the proposed topology with other switched capacitors topologies in terms of total blocking voltage (TBV) and blocking voltage (BV) requirements for an input dc voltage Vin

[137] Reference

[138] NL

[139] TBV

[140] BV

[141] TBV per level

[142] in per unit w.r.t. Vin

[143] BV per level

[144] in per unit w.r.t. Vin

[145] [2]

[146] 5

[147] 9Vin

[148] Vin

[149] 1.800

[150] 0.200

[151] [3]

[152] 5

[153] 11Vin

[154] 2Vin

[155] 2.200

[156] 2.200

[157] [4]

[158] 9

[159] 11Vin

[160] Vin

[161] 1.222

[162] 0.111

[163] [5]

[164] 7

[165] 18Vin

[166] 3Vin

[167] 2.571

[168] 0.428

[169] [6]

[170] 5

[171] 12Vin

[172] 2Vin

[173] 2.400

[174] 0.400

[175] [7]

[176] 7

[177] 16Vin

[178] 2Vin

[179] 2.285

[180] 0.285

[181] [8]

[182] 5

[183] 8Vin

[184] Vin

[185] 1.600

[186] 0.200

[187] [9]

[188] 5

[189] 9Vin

[190] Vin

[191] 1.800

[192] 0.200

[193] [10]

[194] 5

[195] 11Vin

[196] 2Vin

[197] 2.200

[198] 0.400

[199] [11]

[200] 5

[201] 12Vin

[202] 2Vin

[203] 2.400

[204] 0.400

[205] [12]

[206] 5

[207] 20Vin

[208] Vin

[209] 4.000

[210] 0.200

[211] [13]

[212] 5

[213] 9Vin

[214] Vin

[215] 1.800

[216] 0.200

[217] [16]

[218] 9

[219] 10Vin

[220] Vin

[221] 1.111

[222] 0.111

[223] Proposed

[224] 13

[225] 17Vin

[226] 2Vin

[227] 1.307

[228] 0.153

[229] SWITCHING METHODOLOGY

[230] While the proposed topology can be modulated with any of the schemes for multilevel inverters with suitable adaptation, the multicarrier PWM scheme as described in [19] is used in this work as it felicitates the utilization of both the zero states. The scheme is shown in Fig. 3(a). Twelve triangular waveforms Vcrj {j = 1 to 12} of 100Hz frequency each are used as carriers and are configured in phase opposition disposition. A sinusoidal waveform Vref of 50 Hz frequency is taken as the reference signal. These reference and carrier signals are shown in Fig. 3(b). A continuous comparison of the reference with the carriers is carried out. If the reference Vref is greater than carriers, the comparators give 1, 2, 3, 4, 5, 6, 0, -1, -2, -3, -4 and -5 respectively for carriers Vcrj {j = 1 to 12}. On the other hand, if the reference Vref is less than carriers, then comparators give respective outputs as 0,1,2,3,4,5,-1,-2,-3,-4,-5 and -6. Signals aj {j = 1 to 12} are added so as to obtain an aggregated signal ‘a’, shown in Fig. 3(c).

[231] (a)

[232] (b)

[233] (c)

[234] Fig.3. (a) switching scheme for the proposed module; (b) reference and carrier signals; and (c) aggregated signal ‘a’

[235] Aggregated signal ‘a’ has seven positive levels from 15 to 21 in steps of 1 and seven negative levels from -15 to -21 in steps of -1. A one-to-one relationship of these levels in the output waveform is utilized to extract switching pulses (for the specific working states) as shown in Fig. 3(a).

[236] EXPERIMENTAL VERIFICATION

[237] To validate the proposed topology, a laboratory set-up was made using discrete power switch modules (with MOSFETs IRF460 with suitable gate drivers). The input voltage was set to 100V and three capacitors of 2200μF each were used as C1, C2 and C3. dSPACE DS1103 was used to generate real time gate signals. Carrier signals of 100 Hz and reference signal of 50 Hz was used with a modulation index of 0.95. The experimental waveforms are shown in Fig. 4 for an inductive load. The capacitors C1, C2 and C3 are self-balanced at their respective voltages of 100V, 50V and 50V, even when the load current is doubled. The output waveform is a thirteen-level waveform in steps of 50V as expected. Thus, validity of the proposed structure is confirmed in terms of its working and capability of capacitors to be self-balanced.

[238] (a)

[239] (b)

[240] Fig.4. Experimental results: (a) Voltages of capacitors C1, C2 and C3, load voltage and load current; and (b) zoomed waveforms of load voltage and load current

[241] CONCLUSION

[242] A thirteen-level inverter with three-time voltage boosting capability is presented in this paper. The switched capacitors used in the topology are self-balanced and the PIV of all the power switches are significantly less as compared to the operating voltage. A comparative study of the proposed topology with the contemporary topologies indicates its merit in terms of component count and total standing voltage. Experimental results validate the proposed structure. The proposed module can be used for applications which involve low voltage dc sources as input while requiring a high-resolution ac waveform with increased voltage as output.

[243] REFERENCES

[244] D. Abbott, “Keeping the Energy Debate Clean: How Do We Supply the World’s Energy Needs?,” Proc. IEEE,vol. 98, no. 1, pp. 42-66, Jan. 2010.

[245] M. Kanimozhi and P. Geetha, "A new boost switched capacitor multilevel inverter using different multi carrier PWM techniques," 2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014], 2014, pp. 432-437, doi: 10.1109/ICCPCT.2014.7054905.

[246] M. S. W. Chan and K. T. Chau, "A New Switched-Capacitor Boost-Multilevel Inverter Using Partial Charging," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 12, pp. 1145-1149, Dec. 2007, doi: 10.1109/TCSII.2007.905352.

[247] S. S. Lee, “Single-Stage Switched-Capacitor Module (S3CM) Topology for Cascaded Multilevel Inverter,” IEEE Trans. Power Electron.,vol. 33, no. 10, pp. 8204-8207, Oct. 2016.

[248] Y. Hinago and H. Koizumi, “A switched-capacitor inverter using series/parallel conversion with inductive load,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 878-887, Feb. 2012.

[249] Y. Ye, K. W. E. Cheng, J. Liu and K. Ding, “A step-up switched capacitor multilevel inverter with self-voltage balancing,” IEEE Trans. Ind. Electron., vol. 61, no. 12, pp. 6672-6680, Dec. 2014.

[250] X. Sun, B. Wang, Y. Zhou, W. Wang, H. Du and Z. Lu, “A single dc source cascaded seven-level inverter integrating switched-capacitor techniques,” IEEE Trans. Ind. Electron., vol. 63, no. 11, pp. 7184-7194, Nov. 2016.

[251] M. Saeedian, S. M. Hosseini and J. Adabi, “Step-up switched-capacitor module for cascaded MLI topologies,” IET Power Electron., vol. 11, no. 7, pp. 1286-1296, 2016.

[252] E. Babaei and F. Sedaghati, "Series-parallel switched-capacitor based multilevel inverter," 2011 International Conference on Electrical Machines and Systems, 2011, pp. 1-5, doi: 10.1109/ICEMS.2011.6073330.

[253] R. Barzegarkhoo, H. M. Kojabadi, E. Zamiry, N. Vosoughi and L. Chang, "Generalized structure for a single phase switched-capacitor multilevel inverter using a new multiple dc link producer with reduced number of switches,” IEEE Trans. Power Electron., vol. 31, no. 8, pp. 5604-5617, Aug. 2016.

[254] D. A. Ruiz-Caballero, R. M. Ramos-Astudillo, S. A. Mussa and M. L. Heldwein, “Symmetrical hybrid multilevel dc/ac converters with reduced number of insulated dc supplies,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2307-2314, July 2010.

[255] L. He and C. Cheng, “A flying-capacitor-clamped five-level inverter based on bridge modular switched-capacitor topology,” IEEE Trans. Ind. Electron., vol. 63, no. 12, pp. 7814-7822, Dec. 2016.

[256] A. Tsunoda, Y. Hinago and H. Koizumi, "A grid connected inverter with switched capacitor inverter using series/parallel conversion," 2012 15th International Power Electronics and Motion Control Conference (EPE/PEMC), 2012, pp. LS7c.4-1-LS7c.4-5, doi: 10.1109/EPEPEMC.2012.6397513.

[257] Y. Ounejjar, K. Al-Haddad and L. Gregoire, “Packed U Cells Multilevel Converter Topology: Theoretical Study and Experimental Validation,” IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 1294-1306, April 2011.

[258] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu and S. Jain, “Multilevel Inverter Topologies With Reduced Device Count: A Review,” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 135-151, Jan. 2016.

[259] M. B. Kalashani and M. Farsadi, "A new switched-capacitors boost inverter for renewable energy sources and POD control modulation," 2014 22nd Iranian Conference on Electrical Engineering (ICEE), 2014, pp. 636-641, doi: 10.1109/IranianCEE.2014.6999618.

[260] M. F. Kangarlu and E. Babaei, “A generalized cascaded multilevel inverter using series connection of sub-multilevel inverters,” IEEE Trans. Power Electron., vol. 28, no. 2, pp. 625-636, Feb. 2013.

[261] E. Babaei, “A cascade multilevel converter topology with reduced number of switches,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2657-2664, Nov. 2008.

[262] K. K. Gupta and S. Jain, “A novel multilevel inverter based on switched DC sources,” IEEE Trans. Ind. Electron., vol. 61, no. 7, pp. 3269-3278, July 2014.

@article{1700064,
      author = {Niraj Kumar Dewangan, Krishna Kumar Gupta, Pallavee Bhatnagar},
      title = {A Novel Step-Up Multilevel Inverter},
      journal = {Iconic Research And Engineering Journals},
      year = {2017},
      volume = {1},
      number = {4},
      pages = {102-107},
      issn = {2456-8880},
      url = {https://www.irejournals.com/formatedpaper/17000642.pdf},
      abstract = {Switched-capacitors-based multilevel inverters are of two types: single-stage and two-stage. Two-stage topologies require four polarity-reversing switches of high blocking voltage. A single-stage topology is proposed in this work which can synthesize thirteen levels with a single input source and three capacitors, with an overall voltage gain of three. The proposed inverter uses fourteen power switches, of which the blocking voltage of ten switches is restricted to the source voltage. The remaining four switches have blocking voltage equal to twice the source voltage and they operate at low frequency. Thus, for all switches, the blocking voltage is less than the peak output voltage. The proposed module is validated experimentally and the results are presented in this paper. A comparison of the proposed topology with other similar topologies is also presented.},
      keywords = {Multilevel inverter, switched-capacitors, blocking-voltage},
      month = {October},
  }