A Review On Dynamic CMOS Logic Noise Tolerant Techniques

Ankul Gautam; Durgesh Kumar

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A Review On Dynamic CMOS Logic Noise Tolerant Techniques

Ankul Gautam Durgesh Kumar

Subject area: Science,Engineering and Technology · Area of research: Electronics And Communication

Abstract

Dynamic logic vogue is principally used for top fan in and high performance circuits thanks to its smaller space and quick superior speed. This vogue comes with a retardant of low noise margin that makes it a lot of liaable to noise than static CMOS circuits. It conjointly faces some charge sharing and escape issues. A little quantity of noise at the input will cause associate degree undesirable modification at the output. Domino logic (dynamic logic with associate degree electrical converter at the output) conjointly faces this drawback. This paper consist of an summary of assorted noise tolerant techniques for dynamic logic explaining their functioning and responsiveness for combating noise.

Keywords

Delay, Technology, Scaling,Threshold, voltage, Power consumption, Noise, Immunity, Leakage tolerance, Diode flat- footed domino

References

[1] M. Elgebaly and M. Sachdev, “A Leakage Tolerant Energy Efficient Wide Domino Circuit Technique,” IEEE, 2002.

[2] Misbah manzoor, Shekhar verma, Mahwash manzoor,”Noise Tolerant Techniques In Dynamic CMOS Logic,” IEEE 2015.

[3] Rajneesh sharma ,Shekhar verma “comparative analysis of Tatic and dynamic cmos logic design,”IEEE 2011

[4] L. Ding and P. Mazumder, “On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic,”IEEE Transactions on Very Large Scale Integration VLSI Systems, vol.12, no.9, September 2004.

[5] H. Mahmoodi and K. Roy, “Diode-Footed Domino: A Leakage-Tolerant High Fan-in Dynamic Circuit Design Style,”IEEE Transactions on Circuits and Systems, vol.51, no.3, March 2004.

[6] S.Booba and I.N.Hajj, “Design of Dynamic Circuits with Enhanced Noise Tolerance,” IEEE, 1999.

[7] A.Amerabadi, A.Chechelcheraghi et al, “Low Power and High Performance Clock Delayed Domino Logic using Saturated Keeper,” IEEE, 2006.

How to cite this paper

Ankul Gautam , Durgesh Kumar "A Review On Dynamic CMOS Logic Noise Tolerant Techniques" Iconic Research And Engineering Journals Volume 2 Issue 10 2019 Page 11-15

Ankul Gautam , Durgesh Kumar "A Review On Dynamic CMOS Logic Noise Tolerant Techniques" Iconic Research And Engineering Journals, vol. 2, no. 10, Apr. 2019

Ankul Gautam , Durgesh Kumar (2019). A Review On Dynamic CMOS Logic Noise Tolerant Techniques. Iconic Research And Engineering Journals, 2(10).

Ankul Gautam , Durgesh Kumar "A Review On Dynamic CMOS Logic Noise Tolerant Techniques" Iconic Research And Engineering Journals, vol. 2, no. 10, Apr. 2019.

@article{1701109,
      author = {Ankul Gautam , Durgesh Kumar},
      title = {A Review On Dynamic CMOS Logic Noise Tolerant Techniques},
      journal = {Iconic Research And Engineering Journals},
      year = {2019},
      volume = {2},
      number = {10},
      pages = {11-15},
      issn = {2456-8880},
      url = {https://www.irejournals.com/formatedpaper/1701109.pdf},
      abstract = {Dynamic logic vogue is principally used for top fan in and high performance circuits thanks to its smaller  space  and quick superior speed. This vogue comes with a retardant of low noise margin that makes it a lot of liaable to noise than static CMOS circuits. It conjointly faces some charge sharing and escape issues. A little  quantity of noise at the input will cause associate degree undesirable modification at the output. Domino logic (dynamic logic with associate degree electrical converter at the output) conjointly faces this drawback. This paper consist of an summary  of assorted noise tolerant techniques for dynamic  logic explaining their functioning and responsiveness for combating noise.},
      keywords = {Delay, Technology, Scaling,Threshold, voltage, Power consumption, Noise, Immunity, Leakage tolerance, Diode flat- footed domino},
      month = {April},
  }