Effect of Gate Length Scaling on the Electrical Characteristics of a Ge/Si Double-Gate Heterojunction TFET

References

[1] Boucart K, Ionescu AM. Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric. Solid-State Electronics. 2007;51(11–12):1500–1507. https://doi.org/10.1016/j.sse.2007.09.014

[2] Toh EH, Wang GH, Chan L, Yeo YC, Samudra G. Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction. Applied Physics Letters. 2007;91(24):243505. https://doi.org/10.1063/1.2823606

[3] Kurniawan ED, Yang SY, Thirunavukkarasu V, Wu YC. Analysis of Ge-Si heterojunction nanowire tunnel FET: Impact of tunneling window of band-to-band tunneling model. Journal of The Electrochemical Society. 2017;164(6):E3354–E3359. https://doi.org/10.1149/2.0371711jes

[4] Singh R, et al. Simulation analysis of TFETs for low power and high-speed applications. In: Proc. 2024 International Conference on Communication, Computing and Energy Efficient Technologies (I3CEET); 2024. https://doi.org/10.1109/I3CEET61722.2024.10993575

[5] Chen Q, et al. Novel SiGe/Si heterojunction double-gate tunneling FETs with a heterogate dielectric for high performance. Micromachines. 2023;14(4):784. https://doi.org/10.3390/mi14040784

[6] Sharma V, et al. Performance investigation of asymmetric double-gate doping less tunnel FET with Si/Ge heterojunction. IET Circuits, Devices & Systems. 2020;14(6):773–779. https://doi.org/10.1049/iet-cds.2019.0290

[7] Prakash EB, Ray A, Bordoloi S. Strain-engineered Ge-source double-gate TFET with Si/SiGe/Si channel for low-power and THz frequency applications. Scientific Reports. 2026;16:24678. https://doi.org/10.1038/s41598-026-55489-7

[8] Bruel M. Silicon on insulator material technology. Electronics Letters. 1995;31(14):1201–1202. https://doi.org/10.1049/el:19950822

[9] Hisamoto D, Lee WC, Kedzierski J, et al. FinFET—A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices. 2000;47(12):2320–2325. https://doi.org/10.1109/16.887014

[10] Ng HT, Han J, Yamada T, Nguyen P, Chen Y, Meyyappan M. Single crystal nanowire vertical surround-gate field-effect transistor. Nano Letters. 2004;4(7):1247–1252. https://doi.org/10.1021/nl0494610

[11] Reddick W, Amaratunga G. Silicon surface tunnel transistor. Applied Physics Letters. 1995;67(4):494–496. https://doi.org/10.1063/1.114526

[12] Hansch W, Fink C, Schulze J, Eisele I. A vertical MOS-gated Esaki tunneling transistor in silicon. Thin Solid Films. 2000;369(1–2):387–389. https://doi.org/10.1016/S0040-6090(00)00843-1

[13] Wang PF, Hilsenbeck K, Nirschl T, et al. Complementary tunneling transistor for low power application. Solid-State Electronics. 2004;48(12):2281–2286. https://doi.org/10.1016/j.sse.2004.04.004

[14] Khatami Y, Banerjee K. Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy efficient digital circuits. IEEE Transactions on Electron Devices. 2009;56(11):2752–2761. https://doi.org/10.1109/TED.2009.2030831

[15] Choi WY, Park BG, Lee JD, Liu TJK. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Letters. 2007;28(8):743–745. https://doi.org/10.1109/LED.2007.901273

[16] Qin Z, Wei Z, Seabaugh A. Low-subthreshold-swing tunnel transistors. IEEE Electron Device Letters. 2006;27(4):297–290. https://doi.org/10.1109/LED.2006.871855

[17] Li D, Zhang B, Lou H, Zhang L, Lin X, Chan M. Comparative analysis of carrier statistics on MOSFET and tunneling FET characteristics. IEEE Journal of the Electron Devices Society. 2015;3(6):447–451. https://doi.org/10.1109/JEDS.2015.2475143

[18] Chattopadhyay A, Mallik A. Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor. IEEE Transactions on Electron Devices. 2011;58(3):677–683. https://doi.org/10.1109/TED.2010.2099231

[19] Najmzadeh M, Boucart K, Riess W, Ionescu AM. Asymmetrically strained all-silicon multi-gate n-tunnel FETs. Solid-State Electronics. 2010;54(9):935–941. https://doi.org/10.1016/j.sse.2010.04.032

[20] Luisier M, Klimeck G. Atomistic full-band design study of InAs band-to-band tunneling field-effect transistors. IEEE Electron Device Letters. 2009;30(6):602–604. https://doi.org/10.1109/LED.2009.2020443

[21] Saurabh S, Kumar MJ. Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Transactions on Electron Devices. 2011;58(2):404–410. https://doi.org/10.1109/TED.2010.2093142

[22] Bala S, Khosla M. Design and simulation of nanoscale double-gate TFET/tunnel CNTFET. Journal of Computational Electronics. 2018;17(4):1590–1598. https://doi.org/10.1007/s10825-018-1241-2

[23] Kumar S, Goel E, Singh K, Singh B. 2-D analytical modeling of the electrical characteristics of dual-material double-gate TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Transactions on Electron Devices. 2017;64(8):3474–3481. https://doi.org/10.1109/TED.2017.2713834

[24] Noor SL, Safa S, Khan MZR. A silicon-based dual-material double-gate tunnel field-effect transistor with optimized performance. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields. 2017;30(5):e2220. https://doi.org/10.1002/jnm.2220

[25] Silvaco International. ATLAS user’s manual: device simulation software. Vol. II. Santa Clara (CA): Silvaco International; 1998.

@article{1724978,
      author = {Konatham Viswa Teja Punith, Kalapala Prasad, Penjerla Srinivas SubbaRao, Bandi Venkat Chandhan},
      title = {Effect of Gate Length Scaling on the Electrical Characteristics of a Ge/Si Double-Gate Heterojunction TFET},
      journal = {Iconic Research And Engineering Journals},
      year = {2026},
      volume = {10},
      number = {5},
      pages = {2118-2132},
      issn = {2456-8880},
      url = {https://www.irejournals.com/formatedpaper/1724978.pdf},
      abstract = {This paper investigates the effect of gate-length scaling on the electrical characteristics and band-to-band tunneling behavior of a Ge/Si double-gate heterojunction tunnel field-effect transistor (TFET) using Silvaco ATLAS TCAD. Twelve gate lengths ranging from 1 to 20 nm are simulated while the principal device geometry, doping concentrations, gate dielectric thickness, and gate work function are kept constant. The electrical performance is evaluated in terms of ON-state current, OFF-state current, ON/OFF current ratio, threshold voltage, point subthreshold swing, and peak transconductance. The results show that the ON-state current increases from 9.99×10−9 to 1.51×10−4 A as gate length increases from 1 to 20 nm, while the ON/OFF current ratio reaches 1.08×1011. The extracted threshold voltage decreases from 1.24 to 0.46 V, and the point subthreshold swing decreases from 23.42 to 10.00 mV/dec. Peak transconductance reaches 1.63×10−3 S at a gate length of 19 nm before decreasing slightly at 20 nm. Energy-band, electric-field, and nonlocal band-to-band tunneling generation profiles are also examined to support the interpretation of the electrical trends. These findings demonstrate the influence of gate length on the simulated electrical performance and tunneling behavior of the investigated Ge/Si double-gate heterojunction TFET.},
      keywords = {tunnel field-effect transistor (TFET), Ge/Si heterojunction, double-gate transistor, gate-length scaling, Silvaco ATLAS, band-to-band tunneling},
      month = {November},
  }