On-Chip Power Regulator

• Author(s): Teja Jagannatha Naik; Ankita Parulekar; Arpita R Naik; Prasad Poojary; Savitha Acharya
• Paper ID: 1713368
• Page: 1290-1297
• Published Date: 19-01-2026
• Published In: Iconic Research And Engineering Journals
• Publisher: IRE Journals
• e-ISSN: 2456-8880
• Volume/Issue: Volume 9 Issue 7 January-2026

Abstract

Modern SoC and IoT devices demand compact and reliable on-chip voltage regulation, while conventional LDO designs suffer from stability, quiescent power, and bulky external capacitor requirements. This study give a new perspective to overcome this challenge by developing a dual-NMOS, capacitor-less LDO architecture employing a simple CMOS inverter-based control method that eliminates the need for an error amplifier, and automatically adapts to load variations. The design is evaluated through LT-spice simulations using a 180 nm CMOS setup, including transient, DC, and AC analyses of the LDO and its integrated op-amp. It reaches a stable 1.2 V output and shows strong loop stability with an op-amp gain of ~70 dB at a 132? phase margin. Moreover, it offers low quiescent current and clean transient behavior without any off-chip capacitors. These are indications of how the proposed design can achieve great efficiency and stability with minimum Silicon area, suitable for next-generation SoC and sensor power-management systems.

Keywords

Low Dropout Regulator (LDO), NMOS, CMOS inverter, on-chip power management, load regulation, energy efficiency, System on Chip (SoC).

Citations

IRE Journals:
Teja Jagannatha Naik, Ankita Parulekar, Arpita R Naik, Prasad Poojary, Savitha Acharya "On-Chip Power Regulator" Iconic Research And Engineering Journals Volume 9 Issue 7 2026 Page 1290-1297 https://doi.org/10.64388/IREV9I7-1713368

IEEE:
Teja Jagannatha Naik, Ankita Parulekar, Arpita R Naik, Prasad Poojary, Savitha Acharya "On-Chip Power Regulator" Iconic Research And Engineering Journals, 9(7) https://doi.org/10.64388/IREV9I7-1713368