On-Chip Power Regulator

References

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@article{1713368,
      author = {Teja Jagannatha Naik, Ankita Parulekar, Arpita R Naik, Prasad Poojary, Savitha Acharya},
      title = {On-Chip Power Regulator},
      journal = {Iconic Research And Engineering Journals},
      year = {2026},
      volume = {9},
      number = {7},
      pages = {1290-1297},
      issn = {2456-8880},
      url = {https://www.irejournals.com/formatedpaper/1713368.pdf},
      abstract = {Modern SoC and IoT devices demand compact and reliable on-chip voltage regulation, while conventional LDO designs suffer from stability, quiescent power, and bulky external capacitor requirements. This study give a new perspective to overcome this challenge by developing a dual-NMOS, capacitor-less LDO architecture employing a simple CMOS inverter-based control method that eliminates the need for an error amplifier, and automatically adapts to load variations. The design is evaluated through LT-spice simulations using a 180 nm CMOS setup, including transient, DC, and AC analyses of the LDO and its integrated op-amp. It reaches a stable 1.2 V output and shows strong loop stability with an op-amp gain of ~70 dB at a 132? phase margin. Moreover, it offers low quiescent current and clean transient behavior without any off-chip capacitors. These are indications of how the proposed design can achieve great efficiency and stability with minimum Silicon area, suitable for next-generation SoC and sensor power-management systems.},
      keywords = {Low Dropout Regulator (LDO), NMOS, CMOS inverter, on-chip power management, load regulation, energy efficiency, System on Chip (SoC).},
      month = {January},
      doi = {https://doi.org/10.64388/IREV9I7-1713368}
  }