Abstract
This invention concerns the development of an intelligent traffic management system utilizing Very Large Scale Integration (VLSI) concepts to replace traditional hardware-dependent controllers. The traffic control logic is developed using a Finite State Machine (FSM) architecture and implemented in Verilog HDL, providing precise signal timing and reliable state transitions. An embedded simulation environment built on ModelSim ensures real-time logic verification and waveform analysis without the need for expensive physical hardware. The system integrates advanced visualization through a Python-based Graphical User Interface (GUI), which continuously monitors and displays the simulated traffic signal status in real-time. Power consumption and hardware complexities are significantly reduced by utilizing a simulation-first approach. Firmware logic handles sequential state transitions, timer limits, and safety interlocks between conflicting traffic lanes. A modular software design supports scalable traffic intersection layouts and ensures safe, conflict-free signal operation. This invention demonstrates a highly reliable, low-cost, and scalable embedded electronics platform for modern smart city traffic control applications.
Keywords
VLSI design, Finite State Machine (FSM), Verilog HDL, ModelSim Simulation, Python GUI, Smart Traffic Control, Embedded Logic, Waveform Analysis.
Citations
IRE Journals:
S. Lalitha, S. A. Siva, K. K. Tharun, G. Yohendra Prakash "Intelligent Traffic Management System Using VLSI and Python GUI" Iconic Research And Engineering Journals Volume 9 Issue 8 2026 Page 1700-1706
IEEE:
S. Lalitha, S. A. Siva, K. K. Tharun, G. Yohendra Prakash
"Intelligent Traffic Management System Using VLSI and Python GUI" Iconic Research And Engineering Journals, 9(8)
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