Low-Power Design of Approximate Bilateral Filters for Efficient Image Denoising on FPGAs Using Clock Gating

• Author(s): Dr. S K Mahaboob Basha; D. Bhavana; K. Sai Deepika; C H. Pavan; A. Venkata Kiran
• Paper ID: 1715871
• Page: 410-420
• Published Date: 07-04-2026
• Published In: Iconic Research And Engineering Journals
• Publisher: IRE Journals
• e-ISSN: 2456-8880
• Volume/Issue: Volume 9 Issue 10 April-2026

Abstract

This paper presents the design and implementation of a low-power approximate bilateral filtering architecture for efficient image denoising on FPGA platforms, targeting next- generation real-time applications in Industry 5.0 environments. Image denoising plays a crucial role in improving the visual quality of images corrupted by noise introduced during acqui- sition, transmission, or storage. In applications such as medical imaging, autonomous vehicles, surveillance systems, and indus- trial automation, maintaining high image quality while ensuring real-time performance is a major challenge. Traditional filtering techniques such as mean and Gaussian filters are effective in noise reduction but tend to blur edges and fine details. Bilateral filtering, on the other hand, preserves edges by combining spatial and intensity-based filtering, making it highly suitable for advanced image processing applications. However, the computational complexity of bilateral filtering is significantly high due to nonlinear exponential operations, making it inefficient for hardware implementation on FPGA platforms. To address these challenges, this work proposes a novel ap- proximate computing approach that simplifies the mathematical operations involved in bilateral filtering. By replacing complex exponential functions with efficient approximations, the proposed design reduces hardware complexity and improves processing speed. In addition, clock gating techniques are incorporated to minimize dynamic power consumption by reducing unnecessary switching activity in inactive modules. The proposed architecture is also designed to be recon- figurable, enabling it to adapt dynamically to varying noise levels and image characteristics. This flexibility makes it highly suitable for real-world applications where noise conditions are unpredictable. The system supports parallel processing, which further enhances throughput and enables real-time performance. Extensive experimental evaluation is carried out using MAT- LAB for algorithm validation and Xilinx Vivado for hard- ware synthesis and simulation. The results demonstrate that the proposed design achieves significant reductions in power consumption and FPGA resource utilization while maintaining high image quality. Performance metrics such as Peak Signal- to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) confirm that the proposed approximate filter produces results comparable to exact implementations. Overall, the proposed low-power approximate bilateral filter- ing architecture provides an effective balance between perfor- mance, accuracy, and hardware efficiency, making it a promising solution for modern FPGA-based image processing systems.

Citations

IRE Journals:
Dr. S K Mahaboob Basha, D. Bhavana, K. Sai Deepika, C H. Pavan, A. Venkata Kiran "Low-Power Design of Approximate Bilateral Filters for Efficient Image Denoising on FPGAs Using Clock Gating" Iconic Research And Engineering Journals Volume 9 Issue 10 2026 Page 410-420 https://doi.org/10.64388/IREV9I10-1715871

IEEE:
Dr. S K Mahaboob Basha, D. Bhavana, K. Sai Deepika, C H. Pavan, A. Venkata Kiran "Low-Power Design of Approximate Bilateral Filters for Efficient Image Denoising on FPGAs Using Clock Gating" Iconic Research And Engineering Journals, 9(10) https://doi.org/10.64388/IREV9I10-1715871